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vxlib standard cell library | |
Viewable GIF files for the vxlib. This release contains 96 basic inverting and non-inverting gates. Each cell has a typical timing arc and input pin capacitance in 0.13µm generic technology, along with its leakage and dynamic power, size, layout, and the transistor schematic. Transistor sizes are given in lambda, where for this 0.13µm technology, lambda=0.055µm. The cell height is 100 lambda (5.5µm) with power supply rails 12 lambda (0.66µm) wide. The maximum P and N transistor widths before folding are 39λ and 33λ respectively. Cells from the vxlib can be mixed with cells from the ssxlib.
vxlib standard cell physical layout description
description of the vxlib characterisation methodology
an2 standard cell family, vxlib
3× 2-AND gates
an3 standard cell family, vxlib
2× 3-AND gates
an4 standard cell family, vxlib
3× 4-AND gates
aoi21 standard cell family, vxlib
3× 2/1 AND-NOR gates
aoi22 standard cell family, vxlib
3× 2/2 AND-NOR gates
aon21 standard cell family, vxlib
2× 2/1 AND-OR gates
aon22 standard cell family, vxlib
2× 2/2 AND-OR gates
bf1 standard cell family, vxlib
9× non-inverting buffers
cgi2a standard cell family, vxlib
3× carry generator inverting gates with inverted input
cgi2 standard cell family, vxlib
3× carry generator inverting gates
cgn2 standard cell family, vxlib
4× carry generator non-inverting gates
ha2 standard cell family, vxlib
1× 2-bit half adder gates
iv1 standard cell family, vxlib
8× inverters
mxi2 standard cell family, vxlib
2× inverting 2-way muxes
nd2 standard cell family, vxlib
4× 2-NAND gates
nd2a standard cell family, vxlib
2× 2-NAND gates with inverted input
nd2ab standard cell family, vxlib
2× 2-OR gates (faster and larger version using inverters and 2-NAND)
nd3 standard cell family, vxlib
4× 3-NAND gates
nd4 standard cell family, vxlib
4× 4-NAND gates
nr2 standard cell family, vxlib
5× 2-NOR gates
nr3 standard cell family, vxlib
2× 3-NOR gates
nr4 standard cell family, vxlib
2× 4-NOR gates
oai21 standard cell family, vxlib
3× 2/1 OR-NAND gates
oai22 standard cell family, vxlib
3× 2/2 OR-NAND gates
oan21 standard cell family, vxlib
2× 2/1 OR-AND gates
oan22 standard cell family, vxlib
2× 2/2 OR-AND gates
or2 standard cell family, vxlib
1× 2-OR gates
or3 standard cell family, vxlib
1× 3-OR gates
or4 standard cell family, vxlib
1× 4-OR gates
xaoi21 standard cell family, vxlib
2× 2 input exclusive NOR gates with one AND input
xaon21 standard cell family, vxlib
2× 2 input exclusive OR gates with one AND input
xaon22 standard cell family, vxlib
2× 2 input exclusive OR gates with two AND inputs
xnr2 standard cell family, vxlib
2× 2 input exclusive NOR gates
xor2 standard cell family, vxlib
2× 2 input exclusive OR gates