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sxlib standard cell library | |
Viewable GIF files for the Alliance sxlib. This release contains the cells that can be characterised by the scripts in the library: 61 cells in all, combinatorial functions with 1-4 inputs. Each cell has a typical timing arc and input pin capacitance in 0.13µm generic technology, along with its leakage and dynamic power, size, layout, and the transistor schematic. Transistor sizes are given in lambda, where for this 0.13µm technology, lambda=0.055µm. The cell height is 100 lambda (5.5µm) with power supply rails 12 lambda (0.66µm) wide. The maximum P and N transistor widths are 40λ and 34λ respectively.
Note that this lambda value is half the value used in the Alliance sxlib layout. This means that the transistor widths in the cells' schematics are twice the value that will be measured in Graal … e.g. a 40λ transistor will be 20&lambda wide in Graal. Both are 2.2µm wide after conversion to CIF.
The sxlib has been drawn with its own layout rules which means that the 0.13µm layout has plenty of DRC errors. The ssxlib has been derived from the sxlib and has DRC clean layout.
sxlib standard cell physical layout description
description of the vxlib characterisation methodology (used for the sxlib)
a2 standard cell family, sxlib
2× 2-AND gates
a3 standard cell family, sxlib
2× 3-AND gates
a4 standard cell family, sxlib
2× 4-AND gates
an12 standard cell family, sxlib
2× 2-NOR gates with inverted input
ao22 standard cell family, sxlib
2× 2/1 OR-AND gates
ao2o22 standard cell family, sxlib
2× 2/2 OR-AND gates
buf standard cell family, sxlib
3× non-inverting buffers
halfadder standard cell family, sxlib
2× 2-bit half adder gates
inv standard cell family, sxlib
4× inverters
mx2 standard cell family, sxlib
2× non-inverting 2-way muxes
na2 standard cell family, sxlib
2× 2-NAND gates
na3 standard cell family, sxlib
2× 3-NAND gates
na4 standard cell family, sxlib
2× 4-NAND gates
nao22 standard cell family, sxlib
2× 2/1 OR-NAND gates
nao2o22 standard cell family, sxlib
2× 2/2 OR-NAND gates
nmx2 standard cell family, sxlib
2× inverting 2-way muxes
no2 standard cell family, sxlib
2× 2-NOR gates
no3 standard cell family, sxlib
2× 3-NOR gates
no4 standard cell family, sxlib
2× 4-NOR gates
noa22 standard cell family, sxlib
2× 2/1 AND-NOR gates
noa2a22 standard cell family, sxlib
2× 2/2 AND-NOR gates
nxr2 standard cell family, sxlib
2× 2 input exclusive NOR gates
o2 standard cell family, sxlib
2× 2-OR gates
o3 standard cell family, sxlib
2× 3-OR gates
o4 standard cell family, sxlib
2× 4-OR gates
oa22 standard cell family, sxlib
2× 2/1 AND-OR gates
oa2a22 standard cell family, sxlib
2× 2/2 AND-OR gates
on12 standard cell family, sxlib
2× 2-NAND gates with inverted input
xr2 standard cell family, sxlib
2× 2 input exclusive OR gates