Estimated Wireload

Cells are connected by wires which have capacitance which contributes to the circuit delay. Prior to the layout, we estimate this capacitance and hope that it is close to the final value or we will have performance problems. A good and simple estimate is to set the wire cap to each input pin equal to the cap of a standard sized gate input.

In the sclib, which is 42λ tall, we have

A good value for the wire capacitance for each fanout would be 45fF.

We would like the synthesis process to include the delays due to this wireload because

• the delays we see are the realistic delays we can expect to match post-layout
• we want to avoid under buffered netlists with weak gates driving large capacitances

The Alliance synthesis does not handle the concept of a wireload, so we have to add it into the input pin cap of each cell. We do this by copying the VBE library cells to a new directory, adding 45fF to the cin parameter as we do so.

We have a script called makecell which converts a single cell. An entire directory of files can be made by:

$ ls -1 ../sclib100_0/*.vbe | \
  sed 's|^\(.*\)/\(.*\)\.vbe|./makecell \2|' | \
  bash

Note the delimeter '|' used in the sed command which allows an easy use of './' in the replacement expression. To check the difference for the 2-AND gate:

$ diff ../sclib100/a2_y.vbe a2_y.vbe 
<     CONSTANT cin_i1 : NATURAL := 23;  -- cin_i1
<     CONSTANT cin_i0 : NATURAL := 22;  -- cin_i0
---
>   CONSTANT cin_i1        : NATURAL := 68;
>   CONSTANT cin_i0        : NATURAL := 67;

A common problem in general with synthesis is underbuffered gates. By using BOOG and LOON with VBE files that have higher pin capacitances, we try to ensure that the gates are sufficiently buffered.

We repeat the multiplier netlist synthesis with all values of BOOG and LOON, and compare three options for including the 45fF wireload.

• BOOG and LOON with 0fF wireload, retimed at the end with a 45fF wireload
• BOOG with 0fF and LOON with 45fF wireload
• Both BOOG and LOON with 45fF wireloads.

The first synthesis sequence is the previous example with an extra LOON step with opt level=0 to retime with a 45fF wireload.

1 $ ALLIANCE_VBE=$ALLIANCE_MOS/vbe
2 $ MBK_TARGET_LIB=$ALLIANCE_VBE/sclib100_0_min_x8 
3 $ boog -l loon_0000_300_4 multi8 multi8_o
4 $ MBK_TARGET_LIB=$ALLIANCE_VBE/sclib100_0
5 $ loon -l loon_1500_300_2 multi8_o multi8_1
6 $ MBK_TARGET_LIB=$ALLIANCE_VBE/sclib100_45
7 $ loon -l loon_1500_300_0 multi8_1 multi8

The second sequence mimics the previous example but uses a 45fF wireload for the LOON step.

1 $ ALLIANCE_VBE=$ALLIANCE_MOS/vbe
2 $ MBK_TARGET_LIB=$ALLIANCE_VBE/sclib100_0_min_x8 
3 $ boog -l loon_0000_300_4 multi8 multi8_o
4 $ MBK_TARGET_LIB=$ALLIANCE_VBE/sclib100_45
5 $ loon -l loon_1500_300_4 multi8_o multi8  

The third sequence uses 45fF wireloads for BOOG and LOON.

1 $ ALLIANCE_VBE=$ALLIANCE_MOS/vbe
2 $ MBK_TARGET_LIB=$ALLIANCE_VBE/sclib100_45_min_x8
3 $ boog -l loon_0000_300_4 multi8 multi8_o
4 $ MBK_TARGET_LIB=$ALLIANCE_VBE/sclib100_45
5 $ loon -l loon_1500_300_4 multi8_o multi8  

Note that the BOOG library can vary. The fastest netlist uses the min library with the ndrvp inverter for the first option. The other two options use the ndrv inverter.

The full results are on a separate web page.

When we look at the full set of results then we can see that generally the fastest results occur with

• BOOG synthesis with 0fF wireload
• LOON synthesis with 45fF wireload
• BOOG opt level 4
• BOOG synthesis library x8
• LOON opt level 2 or 4