vlsitechnology.org /2LM sclib /synthesis /full results

Estimated Wireload Full Results

Chapter

Section

The three synthesis sequences have been used to generate multiplier netlists with the following timings which include the effects of a 45fF wireload.

BOOG 0fF, LOON 0fF retimed to 45fF
Critical Path Delay (ps)
Opt level BOOG colour coding
LOON 0 1 2 4
0  39514   37968   38244   27658    n1
1  34270   33317   33317   27266    np1
2  30878   29887   29887   23881    ndrv
4  30552   29917   29917   23881    ndrvp

BOOG 0fF, LOON 45fF
Critical Path Delay (ps)
Opt level BOOG colour coding
LOON 0 1 2 4
0  39514   37968   38244   27658    n1
1  31600   31168   31168   27246    np1
2  29267   28484   28484   23331    ndrv
4  29821   28761   28761   22522    ndrvp

BOOG 45fF, LOON 45fF
Critical Path Delay (ps)
Opt level BOOG colour coding
LOON 0 1 2 4
0  39841   38261   38518   30484    n1
1  33721   32853   32729   29791    np1
2  29157   28718   28484   24825    ndrv
4  28978   28700   28204   23122    ndrvp

Each BOOG and LOON synthesis sequence is colour coded to show which BOOG library has been used. The fastest sequence is shown in bold. The fastest opt level is shown in red.

Retiming the netlist produced with a 0fF wireload, we see that the best critical path delay increases from 18119 to 23881, 32% more. Overall, increases are in the range 30%-40%.

Generally the fastest netlists use the x8 BOOG library with a 0fF wireload. Either of LOON opt level 2 or 4 with a 45fF wireload then gives the fastest netlist.

Petley's Law of Power Dissipation

The circuit delay is also where the power is dissipated. The power from the wires should be about equal to the power from the input pins, since we chose the wire cap to be about the same as the input pin cap. Generally too the power from the output node diffusion and metal parasitics is similar to the input pin cap.

Seeing that the wire cap increases the delay by about 1/3, we have Petley's Law of Power Dissipation

  • 25% input pin cap
  • 25% output pin cap
  • 25% wire cap
  • 25% circuitry internal to the cells