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Poly layout design rules

Design rules

No. Description pharosc sxlib scmos-DEEP scmos Generic 0.13µm
vsc vx

3.1

poly width

 2

 2

 2

 2

 2

0.12

3.2

poly space (over field)

 4

 4

 4

 3

 2

0.20

3.2a

poly space (over diffusion, channel space)

 5

 6

 6

 4

 2

0.24

3.3

poly overlap of gate (endcap)

4(5)

4(5)

 3

2.5

 2

0.18(0.20)

3.4

dif overlap of channel (source/drain width)

 5

 5

 4

 4

 3

0.26

3.5

poly – dif space

 2

 2

 2

 1

 1

0.10

3.5a

poly – channel space

 3

 3

 2

 1

 1

0.10

Notes.

  1. DIF is N-diffusion in PWELL or P-diffusion in NWELL. PO is polysilicon.
  2. Rule 3.5 poly-dif space applies for poly to source/drain diffusion and poly to well/substrate tie diffusion.
  3. A rule in parenthesis like 4(5) means 4 is the minimum and 5 is the recommended rule.

poly layout rules
POLY layout design rules