Conclusions

 
IR Drop

• IR drop problem
• Power delivery
• 10% power straps
• standard cell
• chip illustration
• calculate width
• conductivity calc.
• strap width
• 1W core power
• 2W core power
• fixed blocks
• 1W 30% blocks
• 2W 30% RAM, 20% analog
• upper power straps
• die size impact
• examples' die size
• reducing impact
• 1W power best
• 2W power best
• 1W best 30% blocks
• 2W best RAM, analog
• summary of method
• conclusions

 
Derivations

• Vpad derivation
• G(n) derivation
• P(S) derivation
• P(n) derivation
• m(n) derivation

This web paper presents the principles and methodology for calculating the width of power supply straps in an integrated circuit, given the basic design attributes and an estimate of the core power.

This subject matter is largely ignored in the text books that deal with integrated circuit design. For example, In Weste and Eshraghian Principles of CMOS VLSI Design, chapter 4.6 gives an equation for sizing power conductors in order to avoid problems with electromigration, but does not offer any guidance on sizing them for IR drop, even if admitting that normally this is the more serious problem.

The book by Michael J.S. Smith Application-Specific Integrated Circuits simply talks about electromigration and IR drop (in chapter 17.3.2) without offering any advice on how to size the power buses.

I hope that this paper fills a gap in the literature, and will prove useful to you. The same subject matter will appear in my upcoming book The Art of Standard Cell Library Design.